I. Field of the Disclosure
The technology of the disclosure relates generally to communication between a link layer and a physical layer.
II. Background
Computing devices have become common in contemporary society. These computing devices rely on microprocessors and other integrated circuits (ICs). In both mobile computing devices like smart phones and stationary computing devices such as desk top computers, there is a general trend towards decreasing the size of such ICs. As device size decreases, voltages carried on internal voltage rails are also decreased.
While the voltage on the voltage rails in ICs has generally decreased, some ICs include a physical layer (sometimes referred to as a PHY) which requires higher signaling voltages. For example, a system on a chip (SoC) may have a universal serial bus (USB) physical layer designed to communicate with a remote peripheral (e.g., memory, a mouse, a keyboard, or the like). USB generally requires 3.6 volts for signaling. If the voltage rails carry 1.8 volts, a voltage doubler is required if the physical layer remains in the IC. If the voltage rails carry 1.2 volts, a voltage tripler is required if the physical layer remains in the IC. Such voltage multiplying structures are not necessarily reliable.
One solution to the voltage problem is to move the physical layer outside the SoC IC to a separate IC (e.g., a power management integrated circuit (PMIC)) and have a link layer to physical layer bridge between the two ICs. However, many link layer to physical layer protocols require multiple lanes or channels. For example, the USB Transceiver Macrocell Interface (UTMI) has thirty-two (32) channels, and the UTMI+ may have as many as fifty-six (56) channels. Normally a channel requires a dedicated electrical connection (e.g., a wire), and thus, having a USB physical layer removed from the link layer would require thirty-two pins on both the SoC IC and the PHY IC. A typical SoC IC is not able to dedicate this many pins to a relatively minor interface such as USB.
Various solutions have been proposed to address this problem including UTMI+ Low Pin Interface (ULPI), Serial Link PHY Interface (SLPI), and embedded USB2 (eUSB). ULPI still requires eight or twelve pins and has proven to be commercially impractical for IC to IC communication. SLPI requires only two pins, used in a differential mode. However, SLPI defines four signaling methods for register accesses and two signaling methods for data transfer, which has proven to be difficult to manage. Likewise, eUSB uses two pins, which are used in single-ended mode for one type of signaling and differential mode for another type of signaling. State machines track activity to determine what mode is being used. The end result is eUSB has one signaling method for register accesses, two signaling methods for data transfer, and two signaling methods for transfer of control information. The plurality of signaling methods in eUSB is burdensome. Further, SLPI and eUSB define electrical interfaces that require analog circuitry in the SoC IC for functions such as a differential drivers, differential receivers, differential terminations, and squelch detectors. One of the benefits of moving the PHY to the SoC IC is to reduce the amount of analog circuit design required on the SoC IC. By keeping the analog functions on the SoC IC, the benefit of moving the PHY to the SoC IC is not fully realized. Accordingly, there remains a need for a low pin count, simple signaling scheme to allow for link to PHY communication between multiple ICs.